A chip or die may include multiple different regions or areas of circuitry with each of the different areas devoted to different functions. In an embodiment, different areas of circuitry may be referred to as processing units (PUs). For example, in a smartphone or other wireless communication device, a PU may be a wireless baseband modem, a graphics processing unit (GPU), an image processing unit, a core in a multi-core processor, or other type of processing circuitry.
The clock frequency applied to a PU depends on a supply voltage applied to the PU. Throughput and other performance measures of a PU depend on clock frequency. By increasing voltage, higher frequencies may be accommodated, and by decreasing voltage, higher frequency performance may be affected. Thus, adjusting supply voltage is a way to adjust frequency characteristics and thereby the performance of a PU.
Frequency of operation of various PUs on a chip is varied depending on the operating needs of the PUs. For example, watching a movie on a smartphone may demand higher performance of cores on a multi-core processor than when the smartphone is idle and waiting to receive a call. It is therefore useful to incorporate an approximation of the relationship between supply voltage and frequency of operation into determination of the operating point of PUs.
The relationship between supply voltage and frequency of operation may be affected by process variation among different areas of a die. For example, at the time of manufacture of a chip, process variation in manufacturing the transistors in different areas of a chip can result in both chip-to-chip variation in this relationship (inter-chip variation), as well as variation in characteristics of transistors between different areas of a chip (intra-chip variation).
Conventional techniques for ascertaining a relationship between voltage and frequency can include sensors placed on a chip. The sensors provide information about the performance of the region of circuitry in which the sensor resides. For example, the sensors may be designed to capture information about the performance of transistors in circuitry that forms a signal path. The term “critical path” is sometimes used to refer to a signal path having a signal delay that is longer than most or all of the other signal paths of interest on a die or a portion of a die for a set of operating conditions (such as supply voltage and temperature). Thus, setting supply voltage to provide sufficient performance for a critical path can provide some assurance that other signal paths on the same die or same region of the die are operating sufficiently.
An example sensor is a ring oscillator (RO). An example RO comprises a feedback ring having an odd number of inverters with a counter attached to the ring. A RO can be used to generate a clock signal, and the counter can be used to determine process variation effects on frequency characteristics. For example, inverters in a RO may have similar process characteristics as the logic components on a nearby area on the chip, so the RO frequency at a given supply voltage is an indication of performance (e.g., signal delay) of signal paths nearby. Operating frequency of a PU depends on one or more signal delays within the PU, so signal delay provides an indication of the operating frequency of a PU. Higher signal delay indicates lower operating frequency and lower signal delay indicates higher operating frequency.
Conventional sensors account for scenarios in which performance of a signal path is limited primarily by transistor performance. These signal paths are sometimes referred to as gate dominated paths. Some conventional sensors thus take into account characteristics of a first portion of integrated circuit (IC) fabrication where individual devices are patterned in a semiconductor. This first portion of IC fabrication is sometimes referred to the front-end-of-line (FEOL).
However, other factors that affect performance of a signal path are characteristics of wires and vias on the path. Some paths, for example, may include longer wire paths than others, and the paths with longer wires can be affected primarily by wire (and/or via) characteristics, whereas paths with shorter wires can be affected primarily by transistor characteristics. Delays due to transistor characteristics are sometimes referred to as gate delays, and delays due to wire or via characteristics are sometimes referred to as interconnect delays. Paths that are affected primarily by interconnect delays are sometimes referred to as wire dominated paths. In some embodiments, performance of cores in a multi-core processor is affected more by gate dominated paths, and performance of connections between memories and cores is affected more by wire dominated paths. A second portion of IC fabrication adds interconnection among individual devices on a chip, including contacts, interconnect wires, and vias as examples. This second portion of IC fabrication is sometimes referred to as the back-end-of-line (BEOL).
A BEOL sensor can be configured to account for BEOL characteristics. However, BEOL sensors can be quite large, thus sometimes requiring valuable chip area and also making placement of one or more BEOL sensors near a signal path of interest inconvenient in some embodiments. There is thus a need to account for interconnect delay in estimating path delay while employing as few BEOL sensors as feasible.